SMSC DS LAN91C100FD Rev. D
Page 1
Rev. 10/14/2002
PRELIMINARY
LAN91C100FD REV. D
FEAST Fast Ethernet Controller
with Full Duplex Capability
Datasheet
Product Features
Dual Speed CSMA/CD Engine (10 Mbps and 100
Mbps)
Compliant with IEEE 802.3 100BASE-T
Specification
Supports 100BASE-TX, 100BASE-T4, and
10BASE-T Physical Interfaces
32 Bit Wide Data Path (into Packet Buffer
Memory)
Support for 32 and 16 Bit Buses
Support for 32, 16 and 8 Bit CPU Accesses
Synchronous, Asynchronous and Burst DMA
Interface Mode Options
128 Kbyte External
Memory
Built-In Transparent Arbitration for Slave
Sequential Access Architecture
Early TX, Early RX Functions
Flat MMU Architecture with Symmetric Transmit
and Receive Structures and Queues
MII (Media Independent Interface) Compliant
MAC-PHY Interface Running at Nibble Rate
MII Management Serial Interface
Seven Wire Interface to 10 Mbps ENDEC
EEPROM-Based Setup
Full Duplex Capability
ORDERING INFORMATION
Order Numbers:
LAN91C100-FD for 208 Pin QFP Package
LAN91C100-FD for 208 Pin TQFP Package
FEAST Fast Ethernet Controller with Full Duplex Capability
Rev. 10/14/2002
Page 2
SMSC DS LAN91C100FD Rev. D
PRELIMINARY
STANDARD MICROSYSTEMS CORPORATION (SMSC) 2002
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. Product names and company names are the
trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications;
consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is
believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product
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FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS LAN91C100FD Rev. D
Page 3
Rev. 10/14/2002
PRELIMINARY
TABLE OF CONTENTS
Chapter 1
General Description ............................................................................................................. 5
Chapter 2
Pin Configuration................................................................................................................. 6
Chapter 3
Description of Pin Functions ............................................................................................... 7
Chapter 4
Functional Description....................................................................................................... 15
4.1
Description of Block........................................................................................................................... 15
4.1.1
Clock Generator Block............................................................................................................................15
4.2
CSMA/CD BLOCK............................................................................................................................. 15
4.2.1
DMA Block..............................................................................................................................................15
4.2.2
Arbiter Block ...........................................................................................................................................15
4.2.3
MMU Block .............................................................................................................................................16
4.2.4
BIU Block................................................................................................................................................16
4.2.5
MAC-PHY Interface Block ......................................................................................................................16
4.2.6
MII Management Interface Block ............................................................................................................17
4.2.7
Serial EEPROM Interface .......................................................................................................................17
Chapter 5
Data Structures and Registers .......................................................................................... 19
5.1
Packet Format in Buffer Memory ...................................................................................................... 19
5.2
Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 41
5.3
Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 43
5.4
Typical Flow of Events for Receive ................................................................................................... 44
5.5
Memory Partitioning .......................................................................................................................... 49
5.6
Interrupt Generation .......................................................................................................................... 50
Chapter 6
Board Setup Information .................................................................................................. 53
Chapter 7
Application Considerations ............................................................................................... 56
7.1
Fast Ethernet Slave Adapter ............................................................................................................. 56
7.2
VL Local Bus 32 Bit Systems ............................................................................................................ 56
7.3
High End ISA or Non-Burst EISA Machines...................................................................................... 59
7.4
EISA 32 Bit SLAVEEISA 32 Bit Slave............................................................................................... 61
Chapter 8
Operational Description .................................................................................................... 64
8.1
Maximum Guaranteed Ratings* ........................................................................................................ 64
8.2
DC Electrical Characteristics............................................................................................................. 64
Chapter 9
Timing Diagrams................................................................................................................ 67
Chapter 10
Package Outlines............................................................................................................. 77
Chapter 11
LAN91C100FD REV. D Revisions ................................................................................ 79
LIST OF FIGURES
Figure 3.1 - LAN91C100FD Block Diagram .................................................................................................................13
Figure 3.2 - LAN91C100FD System Diagram ..............................................................................................................14
Figure 4.1 - LAN91C100FD Internal Bock diagram with Data Path..............................................................................18
Figure 5.1 - Data Packet Format ..................................................................................................................................19
Figure 5.2 - Interrupt Structure.....................................................................................................................................37
Figure 5.3 - Interrupt Service Routine ..........................................................................................................................45
Figure 5.4 - RX INTR ...................................................................................................................................................46
Figure 5.5 - TX INTR....................................................................................................................................................47
Figure 5.6 - TXEMPTY INTR (Assumes Auto release Option Selected) ......................................................................48
FEAST Fast Ethernet Controller with Full Duplex Capability
Rev. 10/14/2002
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SMSC DS LAN91C100FD Rev. D
PRELIMINARY
Figure 5.7 - Drive Send and Allocate Routines ............................................................................................................49
Figure 5.8 - Interrupt Generation for Transmit, Receive, MMU ....................................................................................52
Figure 6.1 - 64 X 16 Serial EEPROM Map...................................................................................................................55
Figure 7.1 - LAN91C100FD on VL BUS.......................................................................................................................58
Figure 7.2 - LAN91C100FD on ISA Bus.......................................................................................................................60
Figure 7.3 - LAN91C100FD on EISA Bus ....................................................................................................................63
Figure 9.1 - Asynchronous Cycle - nADS=0.................................................................................................................67
Figure 9.2 - Asynchronous Cycle - Using nADS...........................................................................................................68
Figure 9.3 - Asynchronous Cycle - nADS=0.................................................................................................................69
Figure 9.4 - Burst Write Cycles - nVLBUS=1 ...............................................................................................................70
Figure 9.5 - Burst Read Cycles - nVLBUS=1 ...............................................................................................................71
Figure 9.6 - Address Latching for all Modes.................................................................................................................72
Figure 9.7 - Synchronous Write Cycles - nVLBUS=0...................................................................................................72
Figure 9.8 - Synchronous Read Cycle - NVLBUS=0....................................................................................................73
Figure 9.9 - SRAM Interface ........................................................................................................................................74
Figure 9.10 - ENDEC Interface - 10 Mbps ...................................................................................................................75
Figure 9.11 - MII Interface............................................................................................................................................76
Figure 10.1 - 208 Pin QFP Package Outline ................................................................................................................77
Figure 10.2 - 208 Pin TQFP Package Outlines ............................................................................................................78
LIST OF TABLES
Table 3.1 - LAN91C100FD Pin Requirements
12
Table 5.1 - Internal I/O Space Mapping
22
Table 7.1 - VL Local Bus Signal Connections
56
Table 7.2 - High-End ISA or Non-Burst EISA Machines Signal Connectors
59
Table 7.3 - EISA 32 Bit Slave Signal Connections
61
Table 10.1 - 208 Pin QFP Package Parameters
77
Table 10.2 - 208 Pin TQFP Package Outlines
78
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS LAN91C100FD Rev. D
Page 5
Rev. 10/14/2002
PRELIMINARY
Chapter 1 General Description
The LAN91C100FD is designed to facilitate the implementation of first generation Fast Ethernet adapters
and connectivity products. For this first generation of products, flexibility dominates over integration. The
LAN91C100FD is a digital device that implements the MAC portion of the CSMA/CD protocol at 10 and
100 Mbps, and couples it with a lean and fast data and control path system architecture to ensure the CPU
to packet RAM data movement does not cause a bottleneck at 100 Mbps.
Total memory size is 128 Kbytes, equivalent to a total chip storage (transmit plus receive) of 64 outstanding
packets. The LAN91C100FD is software compatible with the LAN9000 family of products and can use existing
LAN9000 drivers (ODI, IPX, and NDIS) in 16 and 32 bit Intel X86 based environments.
Memory management is handled using a unique MMU (Memory Management Unit) architecture and a 32-
bit wide data path. This I/O mapped architecture can sustain back-to-back frame transmission and
reception for superior data throughput and optimal performance. It also dynamically allocates buffer
memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from
performing these housekeeping functions. The total memory size is 128 Kbytes (external), equivalent to a
total chip storage (transmit and receive) of 64 outstanding packets.
FEAST provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus
Interface Unit (BIU) can handle synchronous as well as asynchronous buses, with different signals being
used for each one. FEAST's bus interface supports synchronous buses like the VESA local bus, as well
as burst mode DMA for EISA environments. Asynchronous bus support for ISA is supported even though
ISA cannot sustain 100 Mbps traffic. Fast Ethernet could be adopted for ISA-based nodes on the basis of
the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first is a conventional seven wire ENDEC
interface that connects to the LAN83C694 for 10BASE-T and coax 10 Mbps Ethernet networks. The second
interface follows the MII (Media Independent Interface) specification draft standard, consisting of 4 bit wide
data transfers at the nibble rate. This interface is applicable to 10 Mbps or 100 Mbps networks. Three of the
LAN91C100FD's pins are used to interface to the two-line MII serial management protocol. Four I/O ports
(one input and three output pins) are provided for LAN83C694 configuration.
The LAN91C100FD is based on the LAN91C100 FEAST, functional revision G modified to add full duplex
capability. Also added is a software-controlled option to allow collisions to discard receive packets.
Previously, the LAN91C100 supported a "Diagnostic Full Duplex" mode. Under this mode the transmit
packet is looped internally and received by the MAC. This mode was enabled using the FDUPLX bit in the
TCR. In order to avoid confusion, the new, broader full duplex function of the LAN91C100FD is
designated as Switched Full Duplex, and the TCR bit enabling it is designated as SWFDUP. When the
LAN91C100FD is configured for SWFDUP, its transmit and receive paths will operate independently and
some CSMA/CD functions will be disabled. When the controller is not configured for SWFDUP it will follow
the CSMA/CD protocol.
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